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TENCON 2007 - 2007 IEEE Region 10 Conference
In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction -double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4 x 4 reversible gate called 'HCG' for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG)doi:10.1109/tencon.2007.4428776 fatcat:wy5osg3wq5egrms4vk4guqpxim