Computationally efficient implementation of sparse-tap FIR adaptive filters with tap-position control on Intel IA-32 processors

Akihiro Hirano, Kenji Nakayama
2009 2008 International Symposium on Intelligent Signal Processing and Communications Systems  
This paper presents an computationally efficient implementation of sparse-tap FIR adaptive filters with tapposition control on Intel IA-32 processors with single-instruction multiple-data (SIMD) capability. In order to overcome randomorder memory access which prevents a vectorization, a blockbased processing and a re-ordering buffer are introduced. A dynamic register allocation and the use of memory-to-register operations help the maximization of the loop-unrolling level. Up to 66percent speedup is achieved.
doi:10.1109/ispacs.2009.4806758 fatcat:ke6jsrhlcfesdfykdaek4o2f44