A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

Hao Wu, Gang Jin, Yiqi Zhuang, Wenrui Cao, Lei Bai
2021 IEICE Electronics Express  
A power-efficient Single Event Upset (SEU) -tolerant pulsetriggered flip-flop design is presented. The dual-modular redundant design takes advantage of concise formation of pulse-triggered designs, and avoids the disadvantages of it, such as high power consumption. Clock-gating scheme is applied to reduce power consumption. The static configuration and the avoidance of contention mechanism led to the balance of power consumption, speed and SEU tolerance. The SEU tolerance is evaluated by means
more » ... f SEU cross section, which is significantly lower than conventional D flip-flop. The proposed flip-flop is designed in 55nm CMOS technology to evaluate performances. The proposed design achieves the lowest power consumption, which is even lower than conventional D flip-flop. Although the speed is sacrificed, the lowest power-delay product is achieved among hardened designs. The proposed design provides solution to speedinsensitive and power-constrained applications.
doi:10.1587/elex.18.20210312 fatcat:7haivlz2xjg3xketrtgxbfpq2e