This paper proposes majority-based tracking forecast memories (MTFMs) for area efficient high throughput ASIC implementation of stochastic Low-Density Parity-Check (LDPC) decoders. The proposed method is applied for ASIC implementation of a fully parallel stochastic decoder that decodes the (2048, 1723) LDPC code from the IEEE 802.3an (10GBASE-T) standard. The decoder occupies a silicon core area of 6.38 mm 2 in CMOS 90 nm technology, achieves a maximum clock frequency of 500 MHz, and provides

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... maximum core throughput of 61.3 Gb/s. The decoder also has good decoding performance and error-floor behavior and provides a bit error rate (BER) of about 4 10 13 at 0 = 5.15 dB. To the best of our knowledge, the implemented decoder is the most area efficient fully parallel soft-decision LDPC decoder reported in the literature.