LOW-POWER SRAM CELL FOR EFFICIENT LEAKAGE ENERGY REDUCTION IN DEEP SUBMICRON USING 0.022 µm CMOS TECHNOLOGY

M Reddy, M Sailaja, K Babulu
2018 unpublished
Static Random Access Memory (SRAM) is designed to interface with CPU directly, DSP processors, µprocessors and low-power applications such as handheld devices with long battery life. In order to achieve high-speed performance with low-power, the operating voltage V DD of the SRAM cell is scaled to below 0.8 V. In deep sub-micron CMOS technology, the standard 6T SRAM cell suffers from leakage currents, the stability of the cell, read/write access time and noise transient. Using Dynamic Threshold
more » ... CMOS (DTMOS) technique, an ultra-low voltage circuit (V DD ≤ 0.6 V) in which the substrate of nMOS and pMOS transistors are tied together to the gate terminal. The DTMOS technique reduces the leakage power dissipation in standby mode, whereas the area of the cell is increased. The performance of the 6T-SRAM and DTMOS-SRAM cells is decreased with continuous switching transitions (0 → 1, 1 → 0) of the pull-up and pull-down networks for each bit. We proposed a Hybrid Logic inverter i.e. Pseudo-nMOS-DTMOS based SRAM cell with less energy consumption. The design and implementation of proposed 6T-SRAM cell are compared with standard 6T, Conv. 8T, ST-11T and 6T-DTMOS SRAM cells for 0.3 V supply voltage at 22-nm CMOS technology; which exhibits better performance of the cell. The read and write static noise margin (SNM) of the cell significantly increases, energy consumption of 0.010 fJ and leakage power is 0.02 µW. The layout of the proposed memory cell is drawn in a 45-nm technology, occupies an area of 1.12×greater as compared with 6T-SRAM cell. The layout and performance of the proposed SRAM cell are examined using mentor graphics composer.
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