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LOW-POWER SRAM CELL FOR EFFICIENT LEAKAGE ENERGY REDUCTION IN DEEP SUBMICRON USING 0.022 µm CMOS TECHNOLOGY
2018
unpublished
Static Random Access Memory (SRAM) is designed to interface with CPU directly, DSP processors, µprocessors and low-power applications such as handheld devices with long battery life. In order to achieve high-speed performance with low-power, the operating voltage V DD of the SRAM cell is scaled to below 0.8 V. In deep sub-micron CMOS technology, the standard 6T SRAM cell suffers from leakage currents, the stability of the cell, read/write access time and noise transient. Using Dynamic Threshold
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