Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits

Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu, Wendelin Serwe
2018 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)  
Asynchronous circuits have key advantages in terms of low energy consumption, robustness, and security. However, the absence of a global clock makes the design prone to deadlock, livelock, synchronization, and resource-sharing errors. Formal verification is thus essential for designing such circuits, but it is not widespread enough, as many hardware designers are not familiar with it and few verification tools can cope with asynchrony on complex designs. This paper suggests how an industrial
more » ... ign flow for asynchronous circuits, based upon the standard HDL SystemVerilog, can be supplemented with formal verification capabilities rooted in concurrency theory and modelchecking technology. We demonstrate the practicality of our approach on an industrial asynchronous circuit (4000 lines of SystemVerilog) implementing a memory protection unit.
doi:10.1109/async.2018.00021 dblp:conf/async/BouzafourRG0S18 fatcat:kp56s24fkbdrze56f6qy4hiari