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Exploiting instruction- and data-level parallelism
1997
IEEE Micro
Preserved Fulltext
Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications.
doi:10.1109/40.621210
fatcat:5oanmvkc3vfe7lq3w4jcdbkmjy