Implementation and extensibility of an analytic placer

Andrew B. Kahng, Qinke Wang
2004 Proceedings of the 2004 international symposium on Physical design - ISPD '04  
We examine the general problem of built-in-self-test (BIST) diagnosis in digital logic systems. The BIST diagnosis problem has applications that include identification of erroneous test vectors, faulty scan cells, and faulty items. We develop an abstract model of this problem and show a fundamental correspondence to the well-established subject of combinatorial group testing (CGT) (D. Du and F. K. Hwang, Combinatorial Group Testing and Its Applications, 1994). We exploit this new perspective to
more » ... 1) link existing BIST diagnosis techniques to CGT techniques and provide further insights into existing diagnosis algorithms, 2) improve the performance of diagnosis algorithms, and 3) develop new techniques to address the BIST diagnosis problem. Using the ISCAS'89 benchmarks, we empirically demonstrate the effectiveness of our proposed techniques over existing BIST diagnosis techniques. The vastness of the CGT literature suggests that further improvements from existing research in CGT may be obtained. He has over 20 refereed publications in the areas of physical design, very large scale integrated (VLSI) test and diagnosis, combinatorial optimization, and computer-aided design (CAD) for deoxyribonucleic acid (DNA) chips. Mr. Reda is the recipient of the Best Paper Award at DATE 2002 and the First Place Award at the ISPD 2005 placement contest.
doi:10.1145/981066.981071 dblp:conf/ispd/KahngW04 fatcat:ebyj5axsyzhwdogova3rwhwnqi