Software partitioning of hardware transactions

Lingxiang Xiang, Michael L. Scott
2015 Proceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming - PPoPP 2015  
Best-effort hardware transactional memory (HTM) allows complex operations to execute atomically and in parallel, so long as hardware buffers do not overflow, and conflicts are not encountered with concurrent operations. We describe a programming technique and compiler support to reduce both overflow and conflict rates by partitioning common operations into read-mostly (planning) and write-mostly (completion) operations, which then execute separately. The completion operation remains
more » ... l; planning can often occur in ordinary code. High-level (semantic) atomicity for the overall operation is ensured by passing an applicationspecific validator object between planning and completion. Transparent composition of partitioned operations is made possible through fully-automated compiler support, which migrates all planning operations out of the parent transaction while respecting all program data flow and dependences. For both micro-and macrobenchmarks, experiments on IBM z-Series and Intel Haswell machines demonstrate that partitioning can lead to dramatically lower abort rates and higher scalability.
doi:10.1145/2688500.2688506 dblp:conf/ppopp/XiangS15 fatcat:cixnmibo7bdszmnjr3jmpcruay