A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2013; you can also visit the original URL.
The file type is
The Power of Priority: NoC Based Distributed Cache Coherency
First International Symposium on Networks-on-Chip (NOCS'07)
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Multi Processors (CMPs). We address previously proposed CMP architectures based on Non Uniform Cache Architecture (NUCA) over NoC, analyze basic memory transactions and translate them into a set of network transactions. We first show how a simple, generic NoC which is equipped with needed module interface functionalitiesdoi:10.1109/nocs.2007.42 dblp:conf/nocs/BolotinGCGK07 fatcat:vofomf4eavcgtlcl3po6i2jcga