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<i title="Institute of Electronics, Information and Communications Engineers (IEICE)">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/o6i5xqmqx5cgjj7ri5se4o5bty" style="color: black;">Nonlinear Theory and Its Applications IEICE</a>
PowerSynth has been developed to significantly accelerate power module design through a multi-objective layout synthesis and optimization process. It uses a series of layout generation and optimization algorithms and various electrical and thermal models to automatically synthesize power module layouts and create a Pareto surface of solutions with optimum electrical and thermal performance. Recent advanced power modules are designed with various types of components integrated on multiple device<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/nolta.11.124">doi:10.1587/nolta.11.124</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/sqvepm4ghncyzcodfbukoozggy">fatcat:sqvepm4ghncyzcodfbukoozggy</a> </span>
more »... layers to minimize the parasitics and increase power density. With more compact layouts and tighter design constraints, power module design becomes increasingly challenging because of reliability and signal integrity issues, such as partial discharge, electromagnetic interference (EMI), electro migration, and noise-induced false turn-on. This paper summarizes the latest PowerSynth layout engine and model improvements with an emphasis on the new reliability and signal integrity features. A generic and scalable constraint-aware layout engine is developed to process generic types of devices, traces, and connectors in power modules. Electrical models are improved from a 1D wire model to a 2D mesh model with enhanced feature sets to better capture the intrinsic layout structures and extract coupling between power and gate loops. EMI models are built on top of it to further reduce the noise analysis and qualification requirement posted on designers. Finally, a new post-layout optimization step is included in the flow as an improvement of design for manufacturability and reliability. The software development along with the hardware testing results demonstrates the latest advances in design automation for power electronics.
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