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<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/kesbfldn5jghzhpfukz7ag2zmm" style="color: black;">Microarchitecture (MICRO), Proceedings of the Annual International Symposium on</a>
With the trend towards increasing number of cores in chip multiprocessors, the on-chip interconnect that connects the cores needs to scale efficiently. In this work, we propose the use of high-radix networks in on-chip interconnection networks and describe how the flattened butterfly topology can be mapped to on-chip networks. By using high-radix routers to reduce the diameter of the network, the flattened butterfly offers lower latency and energy consumption than conventional on-chip<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/micro.2007.4408254">doi:10.1109/micro.2007.4408254</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/o5msxpo2arefvhcumlfbx3jvfi">fatcat:o5msxpo2arefvhcumlfbx3jvfi</a> </span>
more »... . In addition, by exploiting the two dimensional planar VLSI layout, the on-chip flattened butterfly can exploit the bypass channels such that non-minimal routing can be used with minimal impact on latency and energy consumption. We evaluate the flattened butterfly and compare it to alternate on-chip topologies using synthetic traffic patterns and traces and show that the flattened butterfly can increase throughput by up to 50% compared to a concentrated mesh and reduce latency by 28% while reducing the power consumption by 38% compared to a mesh network.
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