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This paper describes the large capacity hierarchical branch predictor in the 5.5 GHz IBM zEnterprise EC12 microprocessor. Performance analyses in a simulation model and on zEC12 hardware demonstrate the benefit of this hierarchy compared to a smaller one level predictor. Novel structures and algorithms for two level branch prediction are presented. Prediction information about multiple branches is bulk transferred from the second level into the first upon detecting a perceived miss in the firstdoi:10.1109/hpca.2013.6522308 dblp:conf/hpca/BonannoCLMPS13 fatcat:nxx3skmsv5ek7ifbqoptyua2aq