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A high-performance architecture of arithmetic coder in JPEG2000
2004 IEEE International Conference on Multimedia and Expo (ICME) (IEEE Cat. No.04TH8763)
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This paper presents high-performance architecture of the arithmetic coder for the embedded block coding algorithm in JPEG2000 algorithm. The dedicated pipeline architecture enhanced by the inverse multiple branch selection (IMBS) method is proposed to code two context-symbol pairs per clock cycle. The overall design was implemented in VHDL and synthesized for FPGA devices. Simulation results show that it can process about 17 million samples at 77 MHz working frequency.
doi:10.1109/icme.2004.1394503
fatcat:hzjvodqdhzcrhp2elqkyjr575i