A VLSI design of hierarchical search motion estimation processor chip

Young San Seo, Jae Hee You
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)  
This paper presents a motion estimation processor that has regular and simple structure and achieves 100% hardware utilization without image data fill time. It can compute half-pel precision estimation and I/O is eliminated bottleneck using small distributed on-chip image memory. The number of processing elements is scalable according to the degree of parallel processing and throughput requirements. It has been designed and verified with C++, VHDL.
doi:10.1109/apasic.1999.824075 fatcat:25gpud5ocnalngxrowma7s6zsm