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A VLSI design of hierarchical search motion estimation processor chip
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)
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This paper presents a motion estimation processor that has regular and simple structure and achieves 100% hardware utilization without image data fill time. It can compute half-pel precision estimation and I/O is eliminated bottleneck using small distributed on-chip image memory. The number of processing elements is scalable according to the degree of parallel processing and throughput requirements. It has been designed and verified with C++, VHDL.
doi:10.1109/apasic.1999.824075
fatcat:25gpud5ocnalngxrowma7s6zsm