Workload adaptive shared memory multicore processors with reconfigurable interconnects

Shoaib Akram, Rakesh Kumar, Deming Chen
<span title="">2009</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/z5svl47olzdbvkd77shdahk3fu" style="color: black;">2009 IEEE 7th Symposium on Application Specific Processors</a> </i> &nbsp;
Interconnection networks for multicore processors are designed in a generic way to serve a diversity of workloads. For multicore processors, there is a considerable opportunity to achieve an improvement in performance by implementing interconnects which adapt to different program phases and to a variety of workloads. This paper proposes one such interconnection network for medium-scale (up to 32 cores) shared memory multicore processors and the associated means at the software level to utilize
more &raquo; ... t effectively. The proposed architecture uses clustering to divide the cores on the chip among many groups called clusters. Reconfigurable logic is inserted between clusters to support either isolation or different policies for communication among clusters. The experiments show that the isolation property of clusters can improve overall throughput of a multicore processor by as much as 60% for multiprogramming workloads consisting of two and four applications. The areaoverhead of the additional logic is shown to be minimal.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/sasp.2009.5226329">doi:10.1109/sasp.2009.5226329</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/sasp/AkramKC09.html">dblp:conf/sasp/AkramKC09</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/hdtw4eotx5fuzjaho2k75vjkoe">fatcat:hdtw4eotx5fuzjaho2k75vjkoe</a> </span>
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