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Jittered random sampling with a successive approximation ADC
2014
2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)
This paper proposes a randomly jittered temporal sampling scheme with a successive approximation register (SAR) ADC. The sampling time points are jittered around a uniform sampling clock. A control logic is implemented on a traditional SAR ADC to force it to terminate the sample conversion before reaching the full precision at the jittered time points. As a result, variable word length data samples are produced by the SAR converter. Based on a discrete jittered random sampling theory, this
doi:10.1109/icassp.2014.6853908
dblp:conf/icassp/LuoZ14
fatcat:gppjt4fksje6zespkfxy3got24