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Mitigating the Mismatch between the Coherence Protocol and Conflict Detection in Hardware Transactional Memory
2014
2014 IEEE 28th International Parallel and Distributed Processing Symposium
Hardware Transactional Memory (HTM) usually piggybacks onto the cache coherence protocol to detect data access conflicts between transactions. We identify an intrinsic mismatch between the typical coherence scheme and transaction execution, which causes a sizable amount of unnecessary transaction aborts. This pathological behavior is called false aborting and increases the amount of wasted computation and on-chip communication. For the TM applications we studied, 41% of the transactional write
doi:10.1109/ipdps.2014.69
dblp:conf/ipps/ZhaoCD14
fatcat:cflgqa7jc5bxrfjyd7tn5mwm5a