Runtime Detection of a Bandwidth Denial Attack from a Rogue Network-on-Chip

Rajesh JS, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
2015 Proceedings of the 9th International Symposium on Networks-on-Chip - NOCS '15  
Network-on-Chip, the de-facto industry standard for connecting on-chip components in forthcoming System-on-Chips plays a central role in providing a robust, reliable and secure communication fabric. Conceptual similarities of NoCs to well established computer networks makes the former vulnerable to security threats similar to those confronted during the evolution of computer networks. Further, growing importance of NoC has triggered a constant scrimmage between exploiting new potent security
more » ... eats and identification of techniques to prevent these threats. This work explores a covert threat model for multi-processor system on chips designed using 3rd party NoCs. The proposed malicious NoC can disrupt the availability of on-chip resources, thereby causing large performance bottlenecks for software running on MPSoC platform. This research rationalizes the potency and relevance of such threat and propose techniques that enables a MPSoC integrator to monitor the trustworthiness of the deployed NoC throughout the chip lifetime. Chips with high computational power are the crux of today's pervasive complex digital systems. Microprocessor circuits are evolving towards many core designs with the integration of hundreds of processing cores, memory elements and other devices on a single chip to sustain high performance computing while maintaining low design costs. Two decisive paradigm shifts in the semiconductor industry have made this evolution possible: (a) architectural and (b) organizational. At the heart of the architectural innovation is a scalable high speed data communication structure, the network-on-chip (NoC). NoC is an interconnect network for the glueless integration of on-chip components in the modern complex communication centric designs. In the recent days, NoC has replaced the traditional bus based architecture owing to its structured and modular design, scalability and low design cost. The organizational revolution has resulted in a globalized and collaborative supply chain with pervasive use of third party intellectual properties to reduce the time-to-market and overall design costs. Despite the advantages of these paradigm shifts, modern system-on-chips pose a plethora of security vulnerabilities. This work explores a threat model arising from a malicious NoC IP embedded with a hardware trojan affecting the resource availability of on-chip components. A rigorous simulation infrastructure is established to evaluate v the feasibility and potency of such an attack. Further, a non-invasive runtime monitoring technique is proposed and thoroughly investigated to ensure the trustworthiness of a third party NoC IP with low overheads. vi
doi:10.1145/2786572.2786580 dblp:conf/nocs/SACR15 fatcat:xnd254j74zdwbnfq62osgmz4cm