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This paper proposes a hierarchical relaxed approach to analyze large scale on-chip power/ground (P/G) grids with C4 packages efficiently. Different from the existing hierarchical approach where macro models and time-consuming matrix density reduction technique are used, this novel approach uses an iterative relaxation procedure to explicitly exploit the character of boundary nodes caused by C4 bumps, which can lead to more speedup without losing any accuracy. Also, an efficient partitiondoi:10.1016/j.vlsi.2007.04.003 fatcat:2kqvha2oync3jgk2l3yzyqn2fq