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PowerChop: Identifying and Managing Non-critical Units in Hybrid Processor Architectures
2016
2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)
On-core microarchitectural structures consume significant portions of a processor's power budget. However, depending on application characteristics, those structures do not always provide (much) performance benefit. While timeoutbased power gating techniques have been leveraged for underutilized cores and inactive functional units, these techniques have not directly translated to high-activity units such as vector processing units, complex branch predictors, and caches. The performance benefit
doi:10.1109/isca.2016.22
dblp:conf/isca/LaurenzanoZCTM16
fatcat:bzbr4nle4ngzthlm57gtxgn6oy