PowerChop: Identifying and Managing Non-critical Units in Hybrid Processor Architectures

Michael A. Laurenzano, Yunqi Zhang, Jiang Chen, Lingjia Tang, Jason Mars
2016 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)  
On-core microarchitectural structures consume significant portions of a processor's power budget. However, depending on application characteristics, those structures do not always provide (much) performance benefit. While timeoutbased power gating techniques have been leveraged for underutilized cores and inactive functional units, these techniques have not directly translated to high-activity units such as vector processing units, complex branch predictors, and caches. The performance benefit
more » ... rovided by these units does not necessarily correspond with unit activity, but instead is a function of application characteristics. This work introduces POWERCHOP, a novel technique that leverages the unique capabilities of HW/SW co-designed hybrid processors to enact unit-level power management at the application phase level. POWERCHOP adds two small additional hardware units to facilitate phase identification and triggering different power states, enabling the software layer to cheaply track, predict and take advantage of varying unit criticality across application phases by powering gating units that are not needed for performant execution. Through detailed experimentation, we find that POWERCHOP significantly decreases power consumption, reducing the leakage power of a hybrid server processor by 9% on average (up to 33%) and a hybrid mobile processor by 19% (up to 40%) while introducing just 2% slowdown. Region Cache Criticality Decision Engine Hot Translation Buffer phase signature PVT miss
doi:10.1109/isca.2016.22 dblp:conf/isca/LaurenzanoZCTM16 fatcat:bzbr4nle4ngzthlm57gtxgn6oy