IMPLEMENTATION OF VIRTUAL CHANNEL ROUTER WITH VA AND SA ARBITRATION UNIT USING VHDL

Minakshi M Wanjari, Pankaj Agrawal, Ravi V Kshirsagar
2019 International Journal of Engineering Applied Sciences and Technology  
NoCs are considered the most practicable solution for many-core chips of the future. Router is the backbone of NoC which performs the essential task of guiding and coordinating the data flow and determines the performance to a large extend. This paper focuses on the implementation of virtual channel router which is considered as promising router architecture for NoC. The router consist of static virtual channel buffer architecture, router control logic and crossbar switch. Router control logic
more » ... onsists of virtual channel arbitration unit and switch allocation unit. The source code is written in VHDL. The router is synthesized and simulated using Xilinx ISE Design Suite 13.1. The parameters like area, frequency and delay are calculated from synthesis result. Power is calculated using Xpower analyzer. Average latency and throughput is calculated using Xilinx system generator.
doi:10.33564/ijeast.2019.v04i05.022 fatcat:6ut7xizue5dcld746odjwabqdm