A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2005; you can also visit the original URL.
The file type is application/pdf
.
Efficient error detection, localization, and correction for FPGA-based debugging
2000
Proceedings of the 37th conference on Design automation - DAC '00
Simulations for modern designs are often performed on Field Programmable Gate Array technology in a functional test and debugging process known as emulation, allowing for more complex simulations than possible in software. One drawback to emulation is the lengthy time spent in the back-end CAD tools for each debugging iteration, including debugging changes and the introduction of control and observation logic. We have developed a technique that confines the re-place-and-route area to only the
doi:10.1145/337292.337391
dblp:conf/dac/LachMP00
fatcat:zox77fgunnenbliowsqjxhvtwq