Efficient error detection, localization, and correction for FPGA-based debugging

John Lach, William H. Mangione-Smith, Miodrag Potkonjak
2000 Proceedings of the 37th conference on Design automation - DAC '00  
Simulations for modern designs are often performed on Field Programmable Gate Array technology in a functional test and debugging process known as emulation, allowing for more complex simulations than possible in software. One drawback to emulation is the lengthy time spent in the back-end CAD tools for each debugging iteration, including debugging changes and the introduction of control and observation logic. We have developed a technique that confines the re-place-and-route area to only the
more » ... rtions of the design affected by the introduction of the test logic and by the debugging changes. Therefore, the back-end CAD effort for error detection, localization, and correction is reduced. This benefit is achieved by partitioning the design at the physical level into independent blocks, and the test logic and design changes are localized to the affected blocks. The result is a shortened time between debugging iterations, and thus a shortened time-to-market for the design.
doi:10.1145/337292.337391 dblp:conf/dac/LachMP00 fatcat:zox77fgunnenbliowsqjxhvtwq