Theorem proving techniques are particularly well suited for reasoning about arithmetic above the bit level and for relating di erent levels of abstraction. In this paper we show h o w a non-restoring integer square root algorithm can be transformed to a very e cient hardware implementation. The top level is a Standard ML function that operates on unbounded integers. The bottom level is a structural description of the hardware consisting of an adder subtracter, simple combinational logic and

more »

... registers. Looking at the hardware, it is not at all obvious what function the circuit implements. At the top level, we prove that the algorithm correctly implements the square root function. We then show a series of optimizing transformations that re ne the top level algorithm into the hardware implementation. Each transformation can be veri ed, and in places the transformations are motivated by knowledge about the operands that we can guarantee through veri cation. By decomposing the veri cation e ort into these transformations, we can show that the hardware design implements a square root. We h a ve implemented the algorithm in hardware both as an Altera programmable device and in full-custom CMOS.