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Power Efficiency for Variation-Tolerant Multicore Processors
2006
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design
Challenges in multicore processor design include meeting demands for performance, power, and reliability. The progression towards deep submicron process technologies entails increasing challenges of process variability resulting in timing instabilities and leakage power variation. This work introduces an analytical approach for ensuring timing reliability while meeting the appropriate performance and power demands in spite of process variation. We validate our analytical model using Turandot to
doi:10.1109/lpe.2006.4271854
fatcat:spfo44njvre4rmhfe6urwzicdq