A multi-level design flow for incorporating IP cores: case study of 1D wavelet IP integration

A. Baganne, I. Bennour, M. Elmarzougui, R. Gaiech, E. Martin
2003 Design, Automation and Test in Europe Conference and Exhibition  
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more complex verification problems. In this paper, we present a C++/SystemC based simulation flow at multiple levels of abstraction. Our approach is to use SystemC to describe both application and a set of algorithmic IP cores to be incorporated throughout the design flow. Our methodology supports design refinement through four
more » ... abstraction levels, offers verification techniques at each level and allows the use of EDA coverification tools. The use of C++/SystemC to model all parts of the system provides great flexibility and enables faster simulation compared to existing methodologies. An illustrative case study for wavelet based compression system design shows that our methodology supports efficient algorithmic specification, where IP models can be easily incorporated, modified and simulated in order to quickly evaluate alternative system implementation. Multi-level Simulation Flow The methodology essentially starts with a very high, behaviorallevel design of the system that can be simulated (see Fig 1) . The design process allows: (i) incorporating range of IP models at multiple level of abstraction (ii) system specification refinement and (iii) multi-level simulation. In our case, we used a set of communication principles and design guidance provided by standardization organization VSIA [3] and OSCI [4] . Thus, our design flow is built around four main abstraction levels: Untimed Functional, Timed Functional, Bus cycle accurate and Cycle Accurate levels [8] .
doi:10.1109/date.2003.1253837 fatcat:psl7dn5dr5csvfb5nar4w3cjti