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Towards Designing Asynchronous Microprocessors: From Specification to Tape-out
2019
IEEE Access
Proceeding miniaturization in the VLSI circuits continues to pose challenges to the conventionally used synchronous design style in microprocessors. These include the distribution of clock in the GHz range, robustness to delay variations, reduction in electromagnetic interference, and energy conservation, to name a few. The asynchronous logic has been known for its ability to address the aforementioned challenges by means of the closed-loop handshake protocols, instead of notorious clock
doi:10.1109/access.2019.2903126
fatcat:rwtsay62xbenhn5cgwzszhf4lm