Layout optimizations for double patterning lithography

David Z. Pan, Jae-seok Yang, Kun Yuan, Minsik Cho, Yongchan Ban
2009 2009 IEEE 8th International Conference on ASIC  
Lithography process has become one of the most fundamental limitations for 22nm technology node because of the following reasons: 1) combining immersion and computational lithography, which is the most advanced lithography scheme, may not be enough to be used for 22nm patterning, 2) EUV (Extreme Ultra-Violet) lithography may not be available for mass production in the near future. As a practical solution, pitch doubling technique known as double patterning lithography (DPL) has become a strong
more » ... andidate for 22nm lithography process. Since layout decomposition in DPL plays an important role in addressing the patterning quality, this paper will discuss some recent advancement of decomposition and optimization techniques for DPL friendly layout. We will also discuss the research challenges for double patterning from an EDA perspective.
doi:10.1109/asicon.2009.5351308 fatcat:5xs2ay5snvd4bng6pc6zb33f6y