Computation and communication refinement for multiprocessor SoC design

Radu Marculescu, Umit Y. Ogras, Nicholas H. Zamora
2006 ACM Transactions on Design Automation of Electronic Systems  
Continuous advancements in semiconductor technology enable the design of complex systems-onchips (SoCs) composed of tens or hundreds of IP cores. At the same time, the applications that need to run on such platforms have become increasingly complex and have tight power and performance requirements. Achieving a satisfactory design quality under these circumstances is only possible when both computation and communication refinement are performed efficiently, in an automated and synergistic
more » ... Consequently, formal and disciplined system-level design methodologies are in great demand for future multiprocessor design. This article provides a broad overview of some fundamental research issues and state-of-the-art solutions concerning both computation and communication aspects of system-level design. The methodology we advocate consists of developing abstract application and platform models, followed by application mapping onto the target platform, and then optimizing the overall system via performance analysis. In addition, a communication refinement step is critical for optimizing the communication infrastructure in this multiprocessor setup. Finally, simulation and prototyping can be used for accurate performance evaluation purposes. • 565 memory modules on a single chip are now not only possible but necessary to maintain competitive advantage. Along with these technological advancements, we are witnessing an explosive growth in demand for consumer electronics functionality. These demands result in a push to design portable devices and appliances with only a few months in time-to-market constraints. Systems-on-chips (SoCs) implementing text, speech, and video processing applications are becoming overwhelmingly complex, with digital and analog parts coexisting on the same chip. This trend puts enormous pressure on tool designers to integrate all these parts seamlessly in terms of system synthesis, verification, simulation, and testing. Complementary techniques for system validation, including formal methods and system-level design tools, are therefore crucial in the design of complex embedded systems. Speaking in general terms, a primary goal of system-level design is to minimize the development time and nonrecurrent engineering costs, subject to constraints on performance and functionality of the system. To succeed, both module reuse and system flexibility are key components. At the very heart of the system-level approach is a set of models derived for both applications and platforms, and techniques that can be used to optimize the system at hand. This approach is known as the Y-Chart scheme [Lieverse et al. 2001 ] (Figure 1 ). Referring to Figure 1 , the application models include the workload characterization which is typically expressed in probabilistic terms. These application models must be scalable and flexible enough for quick analysis. Furthermore, it is also crucial to capture the key behavior of the application in the model in order to have confidence in the predicted results. For instance, the application considered herein (namely, MPEG-2 video) is characterized by soft real-time constraints; this implies that occasionally missing deadlines is perfectly acceptable. In real-time systems where the behavior is characterized by hard real-time constraints (e.g., automotive or safety-critical systems) a different set of challenges is posed, both in modeling and analysis; these issues are covered in a companion paper [Eles and Pop, this issue]. From an implementation perspective, the term platform is used for a family of heterogeneous architectures that need to satisfy a set of architectural constraints imposed to allow reuse of hardware and software components [Ferrari and Sangiovanni-Vincentelli 1999] . The platform description may come with some low-level information from designers, depending on the targeted level of accuracy for this type of evaluation. For instance, a platform model can abstract away the cache or other memory effects in order to keep the complexity of the model under control. This is very much the case in Section 2.1, where we focus primarily on the possible interactions between different parts of the application, buffer occupancy, etc. At the same time, the platform model can emphasize communication (as opposed to computation) aspects where communication volume, packet rates, buffer size, etc., represent the information of interest. We make such a distinction, for instance, in Section 3.1, where we try to capture the impact of topology on the overall behavior of the network. Ultimately, from the platform perspective the models we build need to enable accurate analysis in a relative sense, but also need to be simple and flexible enough to allow quick
doi:10.1145/1142980.1142983 fatcat:mqdulmqw5ngmljor6imi5c3z5i