Experimental validation of parallel computation models on the Intel Paragon

B.H.H. Juurlink
Proceedings of the First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing  
Experimental data validating some of the proposed parallel computation models on the Intel Paragon is presented. This architecture is characterized by a large bandwidth and a relatively large startup cost of a message transmission, which makes it extremely important to employ bulk transfers. The models considered are the BSP model, in which it is assumed that all messages have a fixed short size, and the BPRAM, in which block transfers are rewarded.
doi:10.1109/ipps.1998.669961 dblp:conf/ipps/Juurlink98 fatcat:on33zifeafawxn5ovlgmowakbi