A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf
.
Area, power and delay efficient 2-bit magnitude comparator using modified gdi technique in tanner 180nm technology
2018
International Journal of Engineering & Technology
Of late, low power configuration took shape into the mostimportant concentrations in designing the latest VLSI circuits. By considering the same at the maximum priority, another outline of two-bit GDI based Magnitude or Digital Comparator are recommended and actualized with the assistance of Modified GDI transistors. Comparators are building blocks in advanced VLSI configuration circuits. In the current patterns the necessity for occupying less area in chip and low power compact devices. In
doi:10.14419/ijet.v7i2.8.10413
fatcat:lqkdajwppvgo7lnucxbcoen7di