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This paper encompasses the implementation of a novel approach to an 8-bit digital multiplier based on Ancient Indian mathematical algorithm (also known as the Vedic sutra) and its comparison with 2 other conventional multipliers. Since multiplication has become a fundamental function in applications such as Fourier transform, Arithmetic Logic Unit (ALU) architecture and in various sequential clocked circuits, an efficient multiplication technique is a major concern for computer architects. Thedoi:10.17577/ijertv4is060918 fatcat:cg7iui6wonhhzc2fldrrsifx3i