Accurate estimation of parasitic capacitances in analog circuits

A. Agarwal, H. Sampath, V. Yelamanchili, R. Vemuri
Proceedings Design, Automation and Test in Europe Conference and Exhibition  
This paper presents efficient and accurate techniques for modeling parasitic capacitances in analog CMOS circuits. A layout aware synthesis flow using these parasitic models has been proposed. The fast parasitic estimation process replaces the time consuming steps of layout generation and extraction during synthesis. Results indicate that these models are extremely fast and accurate.
doi:10.1109/date.2004.1269090 dblp:conf/date/AgarwalSYV04 fatcat:3bqxwledofa47jvwtzbodsehy4