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Proceedings of the International Symposium on Low Power Electronics and Design
A new LV/LP CMOS four-quadrant analog multiplier designed in a modified bridged-triode scheme (MBTS) is presented. It brings in the benefits in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The fabricated chip in TSMC 0.35µm n-well SPQM CMOS technology has a nonlinearity error less than 0.8% over ±0.5V input range under a nominal supply voltage of ±1.5V, and consumes the total power dissipation of 2.7 mW only.doi:10.1109/lpe.2002.1029609 fatcat:4mjyfasfyfgjtllhwokbukymmu