A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf
.
XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks
2018
2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
Deploying state-of-the-art CNNs requires power-hungry processors and off-chip memory. This precludes the implementation of CNNs in low-power embedded systems. Recent research shows CNNs sustain extreme quantization, binarizing their weights and intermediate feature maps, thereby saving 8-32× memory and collapsing energy-intensive sum-of-products into XNOR-and-popcount operations. We present XNORBIN, a flexible accelerator for binary CNNs with computation tightly coupled to memory for aggressive
doi:10.1109/coolchips.2018.8373076
dblp:conf/coolchips/BahouKACB18
fatcat:cnddwsys7bg45owi5wfdlw2u5y