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One of the biggest stakes in nanoelectronics today is to meet the needs of Artificial Intelligence by designing hardware neural networks which, by fusing computation and memory, process and learn from data with limited energy. For this purpose, memristive devices are excellent candidates to emulate synapses. A challenge, however, is to map existing learning algorithms onto a chip: for a physical implementation, a learning rule should ideally be tolerant to the typical intrinsic imperfections ofdoi:10.1038/s41598-018-38181-3 pmid:30755662 pmcid:PMC6372620 fatcat:tmgmval4ira2ldq5jkgru2vfci