A Parallelized Implementation of Turbo Decoding Based on Network on Chip Multi - core Processor

Chaolong ZHANG, Institute of Microelectronics , Chinese Academy of Sciences, Beijing 10029, China, Zhekun HU, Jie Chen, The 709th Research In stitute of China Shipbuilding Industry Corporation, Wuhan 430009, China, Institute of Microelectronics , Chinese Academy of Sciences, Beijing 10029, China
2014 Journal of Engineering Science and Technology Review  
With the evolution of wireless communication systems, it is increasingly difficult for Application Specific Integrated Circuit (ASIC) solutions to meet the daily changing requirements. A network on chip (NOC) multi-core processor based on message-passing programming model is designed to implement the LTE-A turbo decoder in a parallel mode using pure Software Defined Radio (SDR) approach. The NOC is well balanced between the hardware and software design with a high degree of programmability and
more » ... e-configurability. According to the features of the NOC multi-core processor, the implementation of turbo decoder is optimized to reduce the computational complexity and to increase the parallelization. Several aspects of turbo decoder are investigated in software radio approach rather than hardware. Compared with the results of the software simulation and the Field Programmable Gate Array (FPGA) demonstration, the NOC multicore processor is flexible to realize the proposed turbo decoding algorithm. In addition, our solution has comparable performance with other published ones.
doi:10.25103/jestr.071.09 fatcat:whr5ppbtizdl7fizmhpr6ebhou