Internet Archive Scholar

A Parallelized Implementation of Turbo Decoding Based on Network on Chip Multi - core Processor

Chaolong ZHANG, Institute of Microelectronics , Chinese Academy of Sciences, Beijing 10029, China, Zhekun HU, Jie Chen, The 709th Research In stitute of China Shipbuilding Industry Corporation, Wuhan 430009, China, Institute of Microelectronics , Chinese Academy of Sciences, Beijing 10029, China
2014 Journal of Engineering Science and Technology Review  

Preserved Fulltext

fulltext thumbnail
Web Archive Capture PDF (5.1 MB)
https://web.archive.org/web/20171202222325/http://www.jestr.org/downloads/Volume7Issue1/fulltext97114.pdf

A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL. The file type is application/pdf.

With the evolution of wireless communication systems, it is increasingly difficult for Application Specific Integrated Circuit (ASIC) solutions to meet the daily changing requirements. A network on chip (NOC) multi-core processor based on message-passing programming model is designed to implement the LTE-A turbo decoder in a parallel mode using pure Software Defined Radio (SDR) approach. The NOC is well balanced between the hardware and software design with a high degree of programmability and
more » ... e-configurability. According to the features of the NOC multi-core processor, the implementation of turbo decoder is optimized to reduce the computational complexity and to increase the parallelization. Several aspects of turbo decoder are investigated in software radio approach rather than hardware. Compared with the results of the software simulation and the Field Programmable Gate Array (FPGA) demonstration, the NOC multicore processor is flexible to realize the proposed turbo decoding algorithm. In addition, our solution has comparable performance with other published ones.
doi:10.25103/jestr.071.09 fatcat:whr5ppbtizdl7fizmhpr6ebhou
DOAJ
Citation

Chaolong ZHANG, Institute of Microelectronics , Chinese Academy of Sciences, Beijing 10029, China, Zhekun HU, Jie Chen, The 709th Research In stitute of China Shipbuilding Industry Corporation, Wuhan 430009, China, Institute of Microelectronics , Chinese Academy of Sciences, Beijing 10029, China. "A Parallelized Implementation of Turbo Decoding Based on Network on Chip Multi - core Processor." Journal of Engineering Science and Technology Review 7.1 (2014) 52-59