It has been noted that the majonty of today's telecommunication ASIC's are performing some son of protocol processing or conversion. It has been suggested that a generic. programmable. architecture could replace many of these ASlCs ro reduce costs. and shonen development cycles. reusing this generic processor instead of deveioping new ASICs. This thesis describes a processing architecture which performs generic telrcommunications protocol manipulation. Similar to a DSP processor. this

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... re processes frame streams. providing programmable control for frame manipulation. This thesis offers a proof of concept for this architecture and the design for a prototype. By combining fast. dedicated hardware and slow programmable software. this processor is able to handle highspred transmission links while supponing a wide set of protocols. For implementation purposes. the processor has been tageted for a transmission rate of 2OOMbps. The design has been sirnuliited to 5OMHz in a 0.35 micron ASIC process.