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A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications
2015
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)
In this paper, an over Gb/s stochastic nonbinary LDPC (NB-LDPC) decoder chip is first-reported. The operation of proposed decoder is transformed to logarithm domain, so that the decoding complexity is mitigated by the simpler summations and fewer bit-width. In addition, the storage requirements are dramatically reduced by truncated TFM architecture. After, benefited from architecture optimizations and symbol-serial property, the routing capability of proposed decoder is extraordinarily
doi:10.1109/esscirc.2015.7313837
dblp:conf/esscirc/LeeYCCL15
fatcat:5uh45odwvjgyfnffosogdqhpve