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In this paper, we study real-time in-memory checkpointing as an effective means to improve the reliability of future large-scale parallel processing systems. Under this context, the checkpoint overhead can become a significant performance bottleneck. Novel memory system designs with upcoming non-volatile random access memory (NVRAM) technologies are emerging to address this performance issue. However, we find that those designs can still have prohibitively high checkpoint overhead and systemdoi:10.1145/2751205.2751212 dblp:conf/ics/GaoHX15 fatcat:46qi2vv76fhknoxn3akslrc4xq