Design and Analysis of a Low-Power 8-Bit 500 KS/ S SAR ADC for Bio-Medical Implant Devices DESIGN AND ANALYSIS OF A LOW-POWER 8-BIT 500 KS/S SAR ADC FOR BIO-MEDICAL IMPLANT DEVICES DESIGN AND ANALYSIS OF A LOW-POWER 8-BIT 500 KS/S SAR ADC FOR BIO-MEDICAL IMPLANT DEVICES
DESIGN AND ANALYSIS OF A LOW-POWER 8-BIT 500 KS/S SAR ADC FOR BIO-MEDICAL IMPLANT DEVICES by Ehsan Mazidi The presented thesis is the design and analysis of an 8-bit successive approximation register (SAR) analog to digital convertor (ADC), designed for low-power applications such as bio-medical implants. First we introduce the general concept of analog to digital conversion, different methodologies, and architectures. Later, the SAR architecture, used in this project, is explained in detail.
... lained in detail. The design and analysis of each subsystem for the ADC system has been explained thoroughly. Novel comparator architecture is proposed. This Bulk input comparator substantially reduces the overall power consumption of the ADC system. All the circuits in this project were designed in transistor level using 45 nm CMOS technology. The SAR logic was designed with Verilog and then synthesized to be used in the ADC. The simulations were done in analog mixed signal (AMS) mode. The sampling rate for the designed ADC is 500 KS/s and the power consumption for the SAR ADC system was measured to be 2.1 µW. On account of achieved performance and low power consumption of the designed SAR ADC in this thesis; battery-less bio-implant devices are more feasible than ever. v DEDICATION I would like to dedicate this work to my parents. Without their unconditional love and support I would have never been able to reach this far and achieve this much. I owe them all my success. I love you both. vi ACKNOWLEDGEMENTS