A large number of scientific apllications involve the operation on, and manipulation of sparse matrices. Irregular structure of these matrices, however, causes hardware that otherwise behaves efficient on regular data to severely suffer in performance when handling sparse matrices. In order to tackle this problem, a scheme consisting of a novel Hierarchical Sparse Matrix (HiSM) storage format and an associated architectural concept have been presented. In this paper we propose, describe, and

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... luate a hardware mechanism to facilitate transposition of a sparse matrix stored in the HiSM format. The proposed hardware is meant to be embedded in a vector processor as a functional unit. The main part of the unit consists of an s × s word in-processor memory, where s is the vector processor's section size. We determine the best parametrs for the proposed mechanism and show that it provides for the HiSM-based transposition a speedup in the range from 1.2 to 32.0 times (average 17.6) with respect to the transposition based on the most widely used Compressed Row Storage format.