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A Simulation Study of Decoupled Architecture Computers
1986
IEEE transactions on computers
Decoupled architectures achieve high scalar performance by cleanly splitting instruction processing into memory access and execution tasks. Several decoupled architectures have been proposed, and they all have two characteristics in common: 1) they have two separate sets of instructions, one for accessing memory and one for performing function execution. 2) The memory accessing task and the execution task communicate via architectural queues. These characteristics lead to pipelined computers
doi:10.1109/tc.1986.1676820
fatcat:eosp2gquaff3bf73znsx6iwtw4