The electrical contact of the source and drain regions in state-of-the-art CMOS transistors is nowadays facilitated through NiSi, which is often alloyed with Pt in order to avoid morphological agglomeration of the silicide film. However, the solid-state reaction between as-deposited Ni and the Si substrate exhibits a peculiar change for as-deposited Ni films thinner than a critical thickness of t c =5 nm. Whereas thicker films form polycrystalline NiSi upon annealing above 450 • C, thinner

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... form epitaxial NiSi 2 films which exhibit a high resistance towards agglomeration. For industrial applications, it is therefore of utmost importance to assess the critical thickness with high certainty and find novel methodologies to either increase or decrease its value, depending on the aimed silicide formation. This paper investigates Ni films between 0 and 15 nm initial thickness by using of 'thickness gradients', which provide semi-continuous information on silicide formation and stability as a function of as-deposited layer thickness. The alloying of these Ni layers with 10 % Al, Co, Ge, Pd or Pt renders a significant change in the phase sequence as a function of thickness and dependent on the alloying element. The addition of these ternary impurities therefore change the critical thickness t c . The results are discussed in the framework of