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Lecture Notes in Computer Science
This paper presents an innovative tool used during the verification of the UltraSPARC #IIIi (TM) processor. UltraSparc #IIIi operates in a multi-processor environment. Verifying the robustness of the cache coherency maintaining parts of the design was one of the main challenges facing the functional verification team. The team adopted a combination of standard, "classic" techniques and methodologies, as well as some new innovative approaches. This mixture of old and new led to a well-balanced,doi:10.1007/3-540-36135-9_23 fatcat:ek4rb2nwxnh6vnj75xu4y6a6nq