Innovative Verification Techniques Used in the Implementation of a Third-Generation 1.1GHz 64b Microprocessor [chapter]

Victor Melamed, Harry Stuimer, David Wilkins, Lawrence Chang, Kevin Normoyle, Sutikshan Bhutani
2002 Lecture Notes in Computer Science  
This paper presents an innovative tool used during the verification of the UltraSPARC #IIIi (TM) processor. UltraSparc #IIIi operates in a multi-processor environment. Verifying the robustness of the cache coherency maintaining parts of the design was one of the main challenges facing the functional verification team. The team adopted a combination of standard, "classic" techniques and methodologies, as well as some new innovative approaches. This mixture of old and new led to a well-balanced,
more » ... obust verification flow which enabled finding the majority of the design problems (bugs) early in the pre-silicon stage of the project. This paper discusses an internal tool (Sniper) (patent pending) which increases the processor bus activity in a way which would uncover subtle coherency problems.
doi:10.1007/3-540-36135-9_23 fatcat:ek4rb2nwxnh6vnj75xu4y6a6nq