LOW POWER SYSTEM DESIGN BY COMBINING SOFTWARE PREFETCHING AND DYNAMIC VOLTAGE SCALING

SUMITKUMAR N. PAMNANI, DEEPAK N. AGARWAL, GANG QU, DONALD YEUNG
2007 Journal of Circuits, Systems and Computers  
Performance-enhancement techniques improve CPU speed at the cost of other valuable system resources such as power and energy. Software prefetching is one such tech-21 nique, tolerating memory latency for high performance. In this article, we quantitatively study this technique's impact on system performance and power/energy consumption. 33 nificant performance loss. 14:11 WSPC/123-JCSC 00396 2 S. N. Pamnani et al. systems. Interestingly, many such systems are not hungry for performance since 1
more » ... hey are already "fast enough" to satisfy end-user's desire. For example, the physical limitation of human visual and auditory systems implies that a DVD player 3 does not necessarily need to be implemented using the fastest processor. One natural question is what will be the role, if any, of traditional high-performance techniques 5 such as pipelining, caches, prefetching, and branch prediction in low power system design? We believe that the performance gain achieved by these techniques can be 7 converted into power and energy reduction. We propose a general approach that monitors the performance gain and transfers it into power and energy saving at run-9 time by dynamic voltage scaling (DVS). In this article, we use software prefetching as an example to demonstrate this idea of utilizing high-performance techniques for 11 low power system design. Prefetching 13 Prefetching is a latency tolerance technique, which is generally used to overcome the gap between the (short) processor cycle time and the (long) memory access 15 latency. In prefetching, data is brought to a level of the memory hierarchy that is closer to the processor in advance rather than on demand. This will reduce or 17 eliminate the cache miss penalty and improve performance. More important, it has been regarded as a promising approach for solving the memory wall problem. 1 19 Prefetches can be triggered either by a hardware mechanism, or by a software instruction, or by a combination of both. While hardware prefetching requires extra 21 hardware resources to determine what to prefetch, software prefetching approaches detect data access patterns by static program analysis and allow prefetching to be 23 done selectively and effectively. Several prefetching techniques have been proposed in the past to improve performance. 2-6 However, there has been very little reported 25 on the power and energy overhead associated with prefetching. Dynamic voltage scaling 27 Dynamic voltage scaling is a technique that varies the supply voltage and clock frequency based on the computation load to provide desired performance with the 29 minimal amount of energy consumption. The most practical and well-studied DVS system is the multiple voltage DVS system where a set of predefined discrete volt-31 ages are available simultaneously due to their simplicity of implementation and effectiveness in power reduction. 7-9 In fact, the International Technology Roadmap 33 for Semiconductors has predicted such systems as the trend of future low power systems. 10 35 DVS reduces the operating voltage and thus clock frequency. It saves power and energy at the cost of longer execution time. Therefore, it is applicable only when 37 there exists slack time. That is, the system goes back and forth between "busy" and "idle". When the execution time information is available, there exist optimal 39 algorithms to achieve the maximal energy saving. 8, 9, 11 Without knowing a task's
doi:10.1142/s0218126607003964 fatcat:nggfxz24abe4vpay6ptr5bzp2i