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A new, large scale multiprocessor architecture is presented in this paper. The architecture consists of hierarchies of shared buses and caches. Extended versions of shared bus multicache coherency protocols are used to maintain coherency among all caches in the system. After explaining the basic operation of the strict hierarchical approach, a clustered system is introduced which distributes the memory among groups of processors. Results of simulations are presented which demonstrate that thedoi:10.1145/30350.30378 dblp:conf/isca/Wilson87 fatcat:yyaqljc45fe7ncgymfmmjikf2e