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An evaluation of functional unit lengths for single-chip processors
[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture
When designing a pipelined single-chip processor (SCP) with pipelined functional units of varying length, the processor issue logic must deal with scheduling of the result bus. In order to prevent serious performance degradation due to result bus conflicts, some pipeline scheduling techniques developed in the 1970's may need to be incorporated into the issue logic. Since this is a nontrivial complication of the issue logic, a set of simulations were performed in order to evaluate the
doi:10.1109/micro.1990.151444
fatcat:2rfri25vlrhoniusdodj2zbbki