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Scalable subgraph mapping for acyclic computation accelerators
2006
Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06
Computer architects are constantly faced with the need to improve performance and increase the efficiency of computation in their designs. To this end, it is increasingly common to see acyclic computation accelerators appear in embedded processor designs. One major problem with adding accelerators to a design is that it is difficult to generate high-quality code utilizing them. Hand-written assembly code is typical, and if compiler support does exist, it is implemented using only greedy
doi:10.1145/1176760.1176779
dblp:conf/cases/ClarkHMY06
fatcat:75ei6y23zretlhq4rvdefawg4i