Reliable Design of Three-Dimensional Integrated Circuits

Shengcheng Wang
2018
Hiermit erkläre ich an Eides statt, dass ich die von mir vorgelegte Arbeit selbstständig verfasst habe, dass ich die verwendeten Quellen, Internet-Quellen und Hilfsmittel vollständig angegeben haben und dass ich die Stellen der Arbeit -einschließlich Tabellen, Karten und Abbildungen -die anderen Werken oder dem Internet im Wortlaut oder dem Sinn nach entnommen sind, auf jeden Fall unter Angabe der Quelle als Entlehnung kenntlich gemacht habe. Karlsruhe, Mai 2018 -----------Shengcheng Wang iii
more » ... engcheng Wang iii This page would be intentionally left blank. Abstract Beginning with the invention of the first Integrated Circuit (IC) by Kilby and Noyce in 1959, performance growth in IC is realized primarily by geometrical scaling, which has resulted in a steady doubling of device density from one technology node to another. This observation was famously known as "Moore's law". However, the performance enhancement due to traditional technology scaling has begun to slow down and present diminishing returns due to a number of imminent show-stoppers, including fundamental physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a mismatch between transistors and interconnects regarding size, speed and power. As a result, a new paradigm shift in IC technology and architecture is required to sustain the historical IC performance growth. Three-Dimensional Integrated Circuit (3D IC), which refers to a vertical (or horizontal) stack consisting of multiple ultra-thin IC layers, has emerged as a promising option to overcome the challenges related to conventional geometrical scaling. 3D IC can achieve device density multiplication without aggressive scaling by stacking IC layers in the third dimension. In a 3D IC, multiple IC layers can be vertically/horizontally interconnected by various interconnect techniques, in which Through-Silicon Via (TSV) is a critical one. More specifically, TSV is a vertical electrical connection passing completely through a silicon wafer or die, which is a key enabler for 3D integration. By using TSVs, the interconnection length between stacked IC layers can be significantly reduced compared to conventional two-dimensional counterparts. This reduction further translates into less wire delay and higher performance. However, 3D integration scheme also results in new challenges in the fields of physical design and testing mechanism. In this dissertation, a set of reliability-aware and testability-driven design and optimization techniques have been proposed in order to enable reliable designs of 3D ICs, as well as enhance physical design quality. The first contribution of this dissertation is to develop a holistic Computer-Aided Design (CAD) platform for 3D Power Delivery Network (PDN), which can be integrated seamlessly within commercial electronic design automation development flows. The design of 3D PDN is a constrained optimization problem. An ideal PDN must: i) limit voltage drop which originates in switching circuits transients, and ii) satisfy the constraints that arise from reliability limits. In addition, these problems are further constrained by the requirement to minimize additional hardware overhead introduced by TSVs in 3D ICs. In this dissertation, a CAD platform has been developed to handle the trade-off between 3D PDN design qualities and hardware design cost under the constraints of required reliability metrics. The second contribution of this dissertation is to develop a comprehensive framework for TSV repair in order to enhance yield and improve reliability in 3D ICs. As critiv cal enablers for 3D ICs, TSVs can deliver signals from one layer to another. However, during fabrication and normal operations, they may suffer from various reliability issues. Due to the large number of TSVs in a chip, these issues in turn translate into low yields and reduced lifetimes. In order to fix failed TSVs, a simple but effective way is to add redundant TSVs into 3D designs to increase chip yield and overall reliability with additional hardware overheads. By considering the trade-off between chip qualities (in terms of manufacturing yield and operation lifetime), hardware overhead, and performance, a framework has been proposed to improve chip yield and extend TSV lifetime significantly with well-managed TSV redundancy. The third contribution of this dissertation is to develop a novel test architecture for interposer-based 3D ICs (also knowns as Two-and-a-Half-Dimensional Integrated Circuits (2.5D ICs)), which is emerging as a precursor to TSV-based ones at the present time. In a 2.5D IC, multiple dies are placed side by side on a passive silicon interposer, and all of them must be adequately tested for product qualification. However, due to the special structure of 2.5D IC, new testing challenges have emerged such as: i) reduced number of test pins, ii) higher test power consumption, and iii) increased test-application time. In this dissertation, the research targets the above challenges, and effective solution has been developed to test dies with minimum test cost in terms of power consumption and test-application time. As demands accelerate for increasing device density, higher bandwidths, and lower power consumption, the semiconductor community is focusing on 3D ICs, which promise "More-than-Moore" integration by packing a great deal of functionality into small form factors, while reducing cost and improving performance. However, due to several significant technical hurdles, volume production and commercial exploitation of 3D ICs are not feasible yet, and still in the early phases. For instance, the standard definitions in 3D ICs are still lacking, the supply chain ecosystem is still unstable, and design, verification and test challenges need to be resolved. In this dissertation, we focus on the reliability and testability challenges in 3D IC design. A set of reliability-aware and testability-driven techniques in the aspects of automating the physical-design process for 3D ICs have been proposed. Significant improvements for reliability and performance were demonstrated for 3D ICs. Therefore, the proposed solutions and developed frameworks in this dissertation can act as important building blocks for 3D ICs and push them toward mainstream acceptance in the near future. vi
doi:10.5445/ir/1000083354 fatcat:644at3ogxja2zlyxhbgbng636e